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CST5341A,CST5271A
The CST5341A/5271A series are 4-bit microcontrollers that can play 4-channel melodies or 4-channel ADPCM with PWM direct drive circuits. The resolution of PWM is 8/10/12 bits. They include a low-cost, high-performance CMOS microprocessor. The clock frequency of this rise is usually 8.192 (±3%) MHz.
The chip can operate in a wide voltage range from 2.0V to 5.5V. It contains program ROM (PROM) and data ROM (DROM) internally. The maximum program ROM size is 16K words and the maximum data ROM size is 1024K bytes. The maximum working SRAM is (256+2) notch. It offers a total of 16 software-programmable I/O ports and four output only ports.
The chip can operate in a wide voltage range from 2.0V to 5.5V. It contains program ROM (PROM) and data ROM (DROM) internally. The maximum program ROM size is 16K words and the maximum data ROM size is 1024K bytes. The maximum working SRAM is (256+2) notch. It offers a total of 16 software-programmable I/O ports and four output only ports.
CST5341A/5271A General Description:
The CST5341A/5271A series are 4-bit microcontrollers that can play 4-channel melodies or 4-channel ADPCM with PWM direct drive circuits. The resolution of PWM is 8/10/12 bits. They include a low-cost, high-performance CMOS microprocessor. The clock frequency of this rise is usually 8.192 (±3%) MHz.
The chip can operate in a wide voltage range from 2.0V to 5.5V. It contains program ROM (PROM) and data ROM (DROM) internally. The maximum program ROM size is 16K words and the maximum data ROM size is 1024K bytes. The maximum working SRAM is (256+2) notch. It offers a total of 16 software-programmable I/O ports and four output only ports.
The chip can operate in a wide voltage range from 2.0V to 5.5V. It contains program ROM (PROM) and data ROM (DROM) internally. The maximum program ROM size is 16K words and the maximum data ROM size is 1024K bytes. The maximum working SRAM is (256+2) notch. It offers a total of 16 software-programmable I/O ports and four output only ports.
CST5341A/5271A Features:
Operating voltage: 2.0V to 5.5V
MCU operating frequency: 8.192MHz
Memory size
- Program ROM size: 16K* 12-bit OTP type
- ROM size: 1024K* 8-bit OTP type (Max)
-SRAM size: 256 x 4 bits
- User register: 2 x 4 bits
Wake up function in power off mode:
-HALT mode Wake up source: Ports A, B, D, and E can wake up from HALT mode to normal mode and execute wake up subroutines.
12 input/output pins: Ports A, B, and D can be defined individually as input or output ports.
4 Output only port: port C.
4 Input/Output or 4 input-only port options defined by "Port E" : If input-only ports are used, port E is defined as input-only ports. If the input/output port is selected, port E is defined as the input/output port.
Four reset conditions:
- Low pressure reset. (LVR = 2.0V)
- Power reset.
- External reset pin. (Low activity)
- Watchdog timer overflowed.
An internal interrupt source:
-PWM is interrupted.
WDT
- Watchdog timer, an option that can be enabled/disabled.
- The WDT period is 256 x 256 x 16/Fsys. (System clock=8.192MHz WDT period is 0.13 seconds)
Audio output:
- Support PWM or DAC mode options.
- Support 8/10/12 bits.
Support options are set to pull-down resistance 1M, 50K or 220K ohm, reset pin (PB3 or PC3), low voltage reset, etc.
Oscillator fuse option ±3%, temperature and voltage compensation.
Support for read suppression of security options (1 bit).
Supports 16 level LVD functions.
MCU operating frequency: 8.192MHz
Memory size
- Program ROM size: 16K* 12-bit OTP type
- ROM size: 1024K* 8-bit OTP type (Max)
-SRAM size: 256 x 4 bits
- User register: 2 x 4 bits
Wake up function in power off mode:
-HALT mode Wake up source: Ports A, B, D, and E can wake up from HALT mode to normal mode and execute wake up subroutines.
12 input/output pins: Ports A, B, and D can be defined individually as input or output ports.
4 Output only port: port C.
4 Input/Output or 4 input-only port options defined by "Port E" : If input-only ports are used, port E is defined as input-only ports. If the input/output port is selected, port E is defined as the input/output port.
Four reset conditions:
- Low pressure reset. (LVR = 2.0V)
- Power reset.
- External reset pin. (Low activity)
- Watchdog timer overflowed.
An internal interrupt source:
-PWM is interrupted.
WDT
- Watchdog timer, an option that can be enabled/disabled.
- The WDT period is 256 x 256 x 16/Fsys. (System clock=8.192MHz WDT period is 0.13 seconds)
Audio output:
- Support PWM or DAC mode options.
- Support 8/10/12 bits.
Support options are set to pull-down resistance 1M, 50K or 220K ohm, reset pin (PB3 or PC3), low voltage reset, etc.
Oscillator fuse option ±3%, temperature and voltage compensation.
Support for read suppression of security options (1 bit).
Supports 16 level LVD functions.
The CST5341A is available in SOP8, SOP16, SSOP24 packages:
CST5341A/5271A block diagram:
CST5341A/5271A speaker wake-up structure:
CST5341A/5271A Application Circuit:
Attention:
1. For recording or remote car applications, please refer to the application instructions on the website.
2.C1: 47uF ~ 100uF (depending on application), C2: 0.1uF
3.DAC application circuit does not support PWM wake-up function.
4. For DAC applications, please refer to the application instructions on the website
1. For recording or remote car applications, please refer to the application instructions on the website.
2.C1: 47uF ~ 100uF (depending on application), C2: 0.1uF
3.DAC application circuit does not support PWM wake-up function.
4. For DAC applications, please refer to the application instructions on the website
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