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CST5080A
The CST5080A series is a 4-bit microcontroller that can play 4-channel melodies or 4-channel ADPCM, using PWM direct drive circuit. The PWM resolution is 8/10/12 bits. They include a low-cost, high-performance CMOS microprocessor. The clock frequency for this uplink is typically 8.192 (± 3%) MHz. The chip operates within a wide voltage range of 2.0V to 5.5V and contains a program ROM (PROM) and a data ROM (DROM) internally. The program ROM is 8K words, and the data ROM size is 240K bytes. The maximum working SRAM is (128+2) half bytes. It provides a total of 12 software programmable I/O ports.
CST5080A General Instructions：
he CST5080A series is a 4-bit microcontroller that can play 4-channel melodies or 4-channel ADPCM, using PWM direct drive circuit. The PWM resolution is 8/10/12 bits. They include a low-cost, high-performance CMOS microprocessor. The clock frequency for this uplink is typically 8.192 (± 3%) MHz. The chip operates within a wide voltage range of 2.0V to 5.5V and contains a program ROM (PROM) and a data ROM (DROM) internally. The program ROM is 8K words, and the data ROM size is 240K bytes. The maximum working SRAM is (128+2) half bytes. It provides a total of 12 software programmable I/O ports.
CST5080A Features:
Working voltage: 2.0V to 5.5V
MCU operating frequency: 8.192MHz
Memory size
MCU operating frequency: 8.192MHz
Memory size
Program ROM size: 8K * 12 bit OTP type
Data ROM size: 240K * 8-bit OTP type
SRAM size: 128 * 4 bits
User register: 2 * 4 bits
SRAM size: 128 * 4 bits
User register: 2 * 4 bits
Power off mode wake-up function:
HALT mode wake-up source: Ports A, B, and E/CE can wake up from HALT mode to NORMAL mode and execute wake-up subroutines.。
8 input/output pins: Port A and Port B can be defined bit by bit as input or output ports.
4 input/output ports, or 4 input only ports, or 4 output only ports defined by the option "Ports CE/E/C":
4 input/output ports, or 4 input only ports, or 4 output only ports defined by the option "Ports CE/E/C":
If an input only port is used, port E is defined as an input only port.
If an output only port is used, port C is defined as an output only port.
If the input/output port is selected, the port CE is defined bit by bit as the input/output terminal.
If an output only port is used, port C is defined as an output only port.
If the input/output port is selected, the port CE is defined bit by bit as the input/output terminal.
Four reset conditions:
Low voltage reset. (LVR=2.0 volts)
Power on reset.
External reset pin. (Low activation)
Watch dog timer overflow.
Power on reset.
External reset pin. (Low activation)
Watch dog timer overflow.
一个内部中断源：
PWM interrupt.
WDT
The watchdog timer can be enabled/disabled through options.
The WDT cycle is 256 * 256 * 16/Fsys. (For system clock=8.192MHz, WDT period is 0.13 seconds)
The WDT cycle is 256 * 256 * 16/Fsys. (For system clock=8.192MHz, WDT period is 0.13 seconds)
Audio output:
Support PWM or DAC mo
Supports 8/10/12 bits.
Support options such as pull-down resistor 1M, 50K or 220K ohms, reset pin (PB3 or PC3), low voltage reset, etc.
Oscillator fuse option ± 3%, temperature and voltage compensation.
Support reading prohibited security options (1 digit).
Supports level 16 LVD functionality.
Oscillator fuse option ± 3%, temperature and voltage compensation.
Support reading prohibited security options (1 digit).
Supports level 16 LVD functionality.
CST5080A provides SOP8 and SOP16 packaging：
CST5080A Block Diagram：
CST5080A speaker wake-up structure
CST5080A Port PCE Mode Block Diagram：
CST5080A Application Circuit：
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